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src/cpu/ppc/vm/assembler_ppc.hpp
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rev 13390 : Add useful VSR instructions
and a ldbrx which will be used next by other reviews
@@ -508,12 +508,17 @@
// Vector-Scalar (VSX) instruction support.
LXVD2X_OPCODE = (31u << OPCODE_SHIFT | 844u << 1),
STXVD2X_OPCODE = (31u << OPCODE_SHIFT | 972u << 1),
MTVSRD_OPCODE = (31u << OPCODE_SHIFT | 179u << 1),
+ MTVSRWZ_OPCODE = (31u << OPCODE_SHIFT | 243u << 1),
MFVSRD_OPCODE = (31u << OPCODE_SHIFT | 51u << 1),
MTVSRWA_OPCODE = (31u << OPCODE_SHIFT | 211u << 1),
+ MFVSRWZ_OPCODE = (31u << OPCODE_SHIFT | 115u << 1),
+ XXPERMDI_OPCODE= (60u << OPCODE_SHIFT | 10u << 3),
+ XXMRGHW_OPCODE = (60u << OPCODE_SHIFT | 18u << 3),
+ XXMRGLW_OPCODE = (60u << OPCODE_SHIFT | 50u << 3),
// Vector Permute and Formatting
VPKPX_OPCODE = (4u << OPCODE_SHIFT | 782u ),
VPKSHSS_OPCODE = (4u << OPCODE_SHIFT | 398u ),
VPKSWSS_OPCODE = (4u << OPCODE_SHIFT | 462u ),
@@ -559,10 +564,11 @@
VADDSBS_OPCODE = (4u << OPCODE_SHIFT | 768u ),
VADDSWS_OPCODE = (4u << OPCODE_SHIFT | 896u ),
VADDUBM_OPCODE = (4u << OPCODE_SHIFT | 0u ),
VADDUWM_OPCODE = (4u << OPCODE_SHIFT | 128u ),
VADDUHM_OPCODE = (4u << OPCODE_SHIFT | 64u ),
+ VADDUDM_OPCODE = (4u << OPCODE_SHIFT | 192u ),
VADDUBS_OPCODE = (4u << OPCODE_SHIFT | 512u ),
VADDUWS_OPCODE = (4u << OPCODE_SHIFT | 640u ),
VADDUHS_OPCODE = (4u << OPCODE_SHIFT | 576u ),
VSUBCUW_OPCODE = (4u << OPCODE_SHIFT | 1408u ),
VSUBSHS_OPCODE = (4u << OPCODE_SHIFT | 1856u ),
@@ -1097,20 +1103,23 @@
static int vrb( VectorRegister r) { return vrb(r->encoding());}
static int vrc( VectorRegister r) { return vrc(r->encoding());}
static int vrs( VectorRegister r) { return vrs(r->encoding());}
static int vrt( VectorRegister r) { return vrt(r->encoding());}
+ // Only used on SHA sigma instructions (VX-form)
+ static int vst( int x) { return opp_u_field(x, 16, 16); }
+ static int vsix( int x) { return opp_u_field(x, 20, 17); }
+
// Support Vector-Scalar (VSX) instructions.
- static int vsra( int x) { return opp_u_field(x, 15, 11); }
- static int vsrb( int x) { return opp_u_field(x, 20, 16); }
- static int vsrc( int x) { return opp_u_field(x, 25, 21); }
- static int vsrs( int x) { return opp_u_field(x, 10, 6); }
- static int vsrt( int x) { return opp_u_field(x, 10, 6); }
+ static int vsra( int x) { return opp_u_field(x & 0x1F, 15, 11) | opp_u_field((x & 0x20) >> 5, 29, 29); }
+ static int vsrb( int x) { return opp_u_field(x & 0x1F, 20, 16) | opp_u_field((x & 0x20) >> 5, 30, 30); }
+ static int vsrs( int x) { return opp_u_field(x & 0x1F, 10, 6) | opp_u_field((x & 0x20) >> 5, 31, 31); }
+ static int vsrt( int x) { return vsrs(x); }
+ static int vsdm( int x) { return opp_u_field(x, 23, 22); }
static int vsra( VectorSRegister r) { return vsra(r->encoding());}
static int vsrb( VectorSRegister r) { return vsrb(r->encoding());}
- static int vsrc( VectorSRegister r) { return vsrc(r->encoding());}
static int vsrs( VectorSRegister r) { return vsrs(r->encoding());}
static int vsrt( VectorSRegister r) { return vsrt(r->encoding());}
static int vsplt_uim( int x) { return opp_u_field(x, 15, 12); } // for vsplt* instructions
static int vsplti_sim(int x) { return opp_u_field(x, 15, 11); } // for vsplti* instructions
@@ -2036,10 +2045,11 @@
inline void vaddsbs( VectorRegister d, VectorRegister a, VectorRegister b);
inline void vaddsws( VectorRegister d, VectorRegister a, VectorRegister b);
inline void vaddubm( VectorRegister d, VectorRegister a, VectorRegister b);
inline void vadduwm( VectorRegister d, VectorRegister a, VectorRegister b);
inline void vadduhm( VectorRegister d, VectorRegister a, VectorRegister b);
+ inline void vaddudm( VectorRegister d, VectorRegister a, VectorRegister b);
inline void vaddubs( VectorRegister d, VectorRegister a, VectorRegister b);
inline void vadduws( VectorRegister d, VectorRegister a, VectorRegister b);
inline void vadduhs( VectorRegister d, VectorRegister a, VectorRegister b);
inline void vsubcuw( VectorRegister d, VectorRegister a, VectorRegister b);
inline void vsubshs( VectorRegister d, VectorRegister a, VectorRegister b);
@@ -2111,10 +2121,11 @@
inline void vcmpgtuw_(VectorRegister d, VectorRegister a, VectorRegister b);
inline void vand( VectorRegister d, VectorRegister a, VectorRegister b);
inline void vandc( VectorRegister d, VectorRegister a, VectorRegister b);
inline void vnor( VectorRegister d, VectorRegister a, VectorRegister b);
inline void vor( VectorRegister d, VectorRegister a, VectorRegister b);
+ inline void vmr( VectorRegister d, VectorRegister a);
inline void vxor( VectorRegister d, VectorRegister a, VectorRegister b);
inline void vrld( VectorRegister d, VectorRegister a, VectorRegister b);
inline void vrlb( VectorRegister d, VectorRegister a, VectorRegister b);
inline void vrlw( VectorRegister d, VectorRegister a, VectorRegister b);
inline void vrlh( VectorRegister d, VectorRegister a, VectorRegister b);
@@ -2134,12 +2145,23 @@
// Vector-Scalar (VSX) instructions.
inline void lxvd2x( VectorSRegister d, Register a);
inline void lxvd2x( VectorSRegister d, Register a, Register b);
inline void stxvd2x( VectorSRegister d, Register a);
inline void stxvd2x( VectorSRegister d, Register a, Register b);
+ inline void mtvrwz( VectorRegister d, Register a);
+ inline void mfvrwz( Register a, VectorRegister d);
inline void mtvrd( VectorRegister d, Register a);
inline void mfvrd( Register a, VectorRegister d);
+ inline void xxpermdi( VectorSRegister d, VectorSRegister a, VectorSRegister b, int dm);
+ inline void xxmrghw( VectorSRegister d, VectorSRegister a, VectorSRegister b);
+ inline void xxmrglw( VectorSRegister d, VectorSRegister a, VectorSRegister b);
+
+ // VSX Extended Mnemonics
+ inline void xxspltd( VectorSRegister d, VectorSRegister a, int x);
+ inline void xxmrghd( VectorSRegister d, VectorSRegister a, VectorSRegister b);
+ inline void xxmrgld( VectorSRegister d, VectorSRegister a, VectorSRegister b);
+ inline void xxswapd( VectorSRegister d, VectorSRegister a);
// Vector-Scalar (VSX) instructions.
inline void mtfprd( FloatRegister d, Register a);
inline void mtfprwa( FloatRegister d, Register a);
inline void mffprd( Register a, FloatRegister d);
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