1 /*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2017, SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "memory/resourceArea.hpp"
31 #include "prims/jvm.h"
32 #include "runtime/java.hpp"
33 #include "runtime/os.hpp"
34 #include "runtime/stubCodeGenerator.hpp"
35 #include "utilities/align.hpp"
36 #include "utilities/defaultStream.hpp"
37 #include "utilities/globalDefinitions.hpp"
38 #include "vm_version_ppc.hpp"
39
40 # include <sys/sysinfo.h>
41
42 bool VM_Version::_is_determine_features_test_running = false;
43 uint64_t VM_Version::_dscr_val = 0;
44
45 #define MSG(flag) \
46 if (flag && !FLAG_IS_DEFAULT(flag)) \
47 jio_fprintf(defaultStream::error_stream(), \
48 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
49 " -XX:+" #flag " will be disabled!\n");
50
51 void VM_Version::initialize() {
52
53 // Test which instructions are supported and measure cache line size.
54 determine_features();
55
56 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
57 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
58 if (VM_Version::has_lqarx()) {
59 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8);
60 } else if (VM_Version::has_popcntw()) {
61 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7);
62 } else if (VM_Version::has_cmpb()) {
63 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6);
64 } else if (VM_Version::has_popcntb()) {
65 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5);
66 } else {
67 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0);
68 }
69 }
70
71 bool PowerArchitecturePPC64_ok = false;
72 switch (PowerArchitecturePPC64) {
73 case 8: if (!VM_Version::has_lqarx() ) break;
74 case 7: if (!VM_Version::has_popcntw()) break;
75 case 6: if (!VM_Version::has_cmpb() ) break;
76 case 5: if (!VM_Version::has_popcntb()) break;
77 case 0: PowerArchitecturePPC64_ok = true; break;
78 default: break;
79 }
80 guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to "
81 UINTX_FORMAT " on this machine", PowerArchitecturePPC64);
82
83 // Power 8: Configure Data Stream Control Register.
84 if (PowerArchitecturePPC64 >= 8 && has_mfdscr()) {
85 config_dscr();
86 }
87
88 if (!UseSIGTRAP) {
89 MSG(TrapBasedICMissChecks);
90 MSG(TrapBasedNotEntrantChecks);
91 MSG(TrapBasedNullChecks);
92 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false);
93 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false);
94 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false);
95 }
96
97 #ifdef COMPILER2
98 if (!UseSIGTRAP) {
99 MSG(TrapBasedRangeChecks);
100 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false);
101 }
102
103 // On Power6 test for section size.
104 if (PowerArchitecturePPC64 == 6) {
105 determine_section_size();
106 // TODO: PPC port } else {
107 // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
108 }
109
110 MaxVectorSize = 8;
111 #endif
112
113 // Create and print feature-string.
114 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
115 jio_snprintf(buf, sizeof(buf),
116 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
117 (has_fsqrt() ? " fsqrt" : ""),
118 (has_isel() ? " isel" : ""),
119 (has_lxarxeh() ? " lxarxeh" : ""),
120 (has_cmpb() ? " cmpb" : ""),
121 //(has_mftgpr()? " mftgpr" : ""),
122 (has_popcntb() ? " popcntb" : ""),
123 (has_popcntw() ? " popcntw" : ""),
124 (has_fcfids() ? " fcfids" : ""),
125 (has_vand() ? " vand" : ""),
126 (has_lqarx() ? " lqarx" : ""),
127 (has_vcipher() ? " aes" : ""),
128 (has_vpmsumb() ? " vpmsumb" : ""),
129 (has_tcheck() ? " tcheck" : ""),
130 (has_mfdscr() ? " mfdscr" : ""),
131 (has_vsx() ? " vsx" : ""),
132 (has_ldbrx() ? " ldbrx" : ""),
133 (has_stdbrx() ? " stdbrx" : "")
134 // Make sure number of %s matches num_features!
135 );
136 _features_string = os::strdup(buf);
137 if (Verbose) {
138 print_features();
139 }
140
141 // PPC64 supports 8-byte compare-exchange operations (see
142 // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr)
143 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
144 _supports_cx8 = true;
145
146 // Used by C1.
147 _supports_atomic_getset4 = true;
148 _supports_atomic_getadd4 = true;
149 _supports_atomic_getset8 = true;
150 _supports_atomic_getadd8 = true;
151
152 UseSSE = 0; // Only on x86 and x64
153
154 intx cache_line_size = L1_data_cache_line_size();
155
156 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
157
158 if (AllocatePrefetchStyle == 4) {
159 AllocatePrefetchStepSize = cache_line_size; // Need exact value.
160 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.
161 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?
162 } else {
163 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
164 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value.
165 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined?
166 }
167
168 assert(AllocatePrefetchLines > 0, "invalid value");
169 if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
170 AllocatePrefetchLines = 1; // Conservative value.
171 }
172
173 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
174 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
175 }
176
177 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
178
179 // If defined(VM_LITTLE_ENDIAN) and running on Power8 or newer hardware,
180 // the implementation uses the vector instructions available with Power8.
181 // In all other cases, the implementation uses only generally available instructions.
182 if (!UseCRC32Intrinsics) {
183 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
184 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
185 }
186 }
187
188 // Implementation does not use any of the vector instructions available with Power8.
189 // Their exploitation is still pending (aka "work in progress").
190 if (!UseCRC32CIntrinsics) {
191 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
192 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
193 }
194 }
195
196 // TODO: Provide implementation.
197 if (UseAdler32Intrinsics) {
198 warning("Adler32Intrinsics not available on this CPU.");
199 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
200 }
201
202 // The AES intrinsic stubs require AES instruction support.
203 #if defined(VM_LITTLE_ENDIAN)
204 if (has_vcipher()) {
205 if (FLAG_IS_DEFAULT(UseAES)) {
206 UseAES = true;
207 }
208 } else if (UseAES) {
209 if (!FLAG_IS_DEFAULT(UseAES))
210 warning("AES instructions are not available on this CPU");
211 FLAG_SET_DEFAULT(UseAES, false);
212 }
213
214 if (UseAES && has_vcipher()) {
215 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
216 UseAESIntrinsics = true;
217 }
218 } else if (UseAESIntrinsics) {
219 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
220 warning("AES intrinsics are not available on this CPU");
221 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
222 }
223
224 #else
225 if (UseAES) {
226 warning("AES instructions are not available on this CPU");
227 FLAG_SET_DEFAULT(UseAES, false);
228 }
229 if (UseAESIntrinsics) {
230 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
231 warning("AES intrinsics are not available on this CPU");
232 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
233 }
234 #endif
235
236 if (UseAESCTRIntrinsics) {
237 warning("AES/CTR intrinsics are not available on this CPU");
238 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
239 }
240
241 if (UseGHASHIntrinsics) {
242 warning("GHASH intrinsics are not available on this CPU");
243 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
244 }
245
246 if (FLAG_IS_DEFAULT(UseFMA)) {
247 FLAG_SET_DEFAULT(UseFMA, true);
248 }
249
250 if (UseSHA) {
251 warning("SHA instructions are not available on this CPU");
252 FLAG_SET_DEFAULT(UseSHA, false);
253 }
254 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
255 warning("SHA intrinsics are not available on this CPU");
256 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
257 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
258 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
259 }
260
261 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
262 UseSquareToLenIntrinsic = true;
263 }
264 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
265 UseMulAddIntrinsic = true;
266 }
267 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
268 UseMultiplyToLenIntrinsic = true;
269 }
270 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
271 UseMontgomeryMultiplyIntrinsic = true;
272 }
273 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
274 UseMontgomerySquareIntrinsic = true;
275 }
276
277 if (UseVectorizedMismatchIntrinsic) {
278 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
279 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
280 }
281
282
283 // Adjust RTM (Restricted Transactional Memory) flags.
284 if (UseRTMLocking) {
285 // If CPU or OS are too old:
286 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
287 // setting during arguments processing. See use_biased_locking().
288 // VM_Version_init() is executed after UseBiasedLocking is used
289 // in Thread::allocate().
290 if (!has_tcheck()) {
291 vm_exit_during_initialization("RTM instructions are not available on this CPU");
292 }
293 bool os_too_old = true;
294 #ifdef AIX
295 // Actually, this is supported since AIX 7.1.. Unfortunately, this first
296 // contained bugs, so that it can only be enabled after AIX 7.1.3.30.
297 // The Java property os.version, which is used in RTM tests to decide
298 // whether the feature is available, only knows major and minor versions.
299 // We don't want to change this property, as user code might depend on it.
300 // So the tests can not check on subversion 3.30, and we only enable RTM
301 // with AIX 7.2.
302 if (os::Aix::os_version() >= 0x07020000) { // At least AIX 7.2.
303 os_too_old = false;
304 }
305 #endif
306 #ifdef LINUX
307 // At least Linux kernel 4.2, as the problematic behavior of syscalls
308 // being called in the middle of a transaction has been addressed.
309 // Please, refer to commit b4b56f9ecab40f3b4ef53e130c9f6663be491894
310 // in Linux kernel source tree: https://goo.gl/Kc5i7A
311 if (os::Linux::os_version_is_known()) {
312 if (os::Linux::os_version() >= 0x040200)
313 os_too_old = false;
314 } else {
315 vm_exit_during_initialization("RTM can not be enabled: kernel version is unknown.");
316 }
317 #endif
318 if (os_too_old) {
319 vm_exit_during_initialization("RTM is not supported on this OS version.");
320 }
321 }
322
323 if (UseRTMLocking) {
324 #if INCLUDE_RTM_OPT
325 if (!UnlockExperimentalVMOptions) {
326 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. "
327 "It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
328 } else {
329 warning("UseRTMLocking is only available as experimental option on this platform.");
330 }
331 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
332 // RTM locking should be used only for applications with
333 // high lock contention. For now we do not use it by default.
334 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
335 }
336 #else
337 // Only C2 does RTM locking optimization.
338 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
339 // setting during arguments processing. See use_biased_locking().
340 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
341 #endif
342 } else { // !UseRTMLocking
343 if (UseRTMForStackLocks) {
344 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
345 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
346 }
347 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
348 }
349 if (UseRTMDeopt) {
350 FLAG_SET_DEFAULT(UseRTMDeopt, false);
351 }
352 if (PrintPreciseRTMLockingStatistics) {
353 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
354 }
355 }
356
357 // This machine allows unaligned memory accesses
358 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
359 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
360 }
361 }
362
363 bool VM_Version::use_biased_locking() {
364 #if INCLUDE_RTM_OPT
365 // RTM locking is most useful when there is high lock contention and
366 // low data contention. With high lock contention the lock is usually
367 // inflated and biased locking is not suitable for that case.
368 // RTM locking code requires that biased locking is off.
369 // Note: we can't switch off UseBiasedLocking in get_processor_features()
370 // because it is used by Thread::allocate() which is called before
371 // VM_Version::initialize().
372 if (UseRTMLocking && UseBiasedLocking) {
373 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
374 FLAG_SET_DEFAULT(UseBiasedLocking, false);
375 } else {
376 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
377 UseBiasedLocking = false;
378 }
379 }
380 #endif
381 return UseBiasedLocking;
382 }
383
384 void VM_Version::print_features() {
385 tty->print_cr("Version: %s L1_data_cache_line_size=%d", features_string(), L1_data_cache_line_size());
386 }
387
388 #ifdef COMPILER2
389 // Determine section size on power6: If section size is 8 instructions,
390 // there should be a difference between the two testloops of ~15 %. If
391 // no difference is detected the section is assumed to be 32 instructions.
392 void VM_Version::determine_section_size() {
393
394 int unroll = 80;
395
396 const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord;
397
398 // Allocate space for the code.
399 ResourceMark rm;
400 CodeBuffer cb("detect_section_size", code_size, 0);
401 MacroAssembler* a = new MacroAssembler(&cb);
402
403 uint32_t *code = (uint32_t *)a->pc();
404 // Emit code.
405 void (*test1)() = (void(*)())(void *)a->function_entry();
406
407 Label l1;
408
409 a->li(R4, 1);
410 a->sldi(R4, R4, 28);
411 a->b(l1);
412 a->align(CodeEntryAlignment);
413
414 a->bind(l1);
415
416 for (int i = 0; i < unroll; i++) {
417 // Schleife 1
418 // ------- sector 0 ------------
419 // ;; 0
420 a->nop(); // 1
421 a->fpnop0(); // 2
422 a->fpnop1(); // 3
423 a->addi(R4,R4, -1); // 4
424
425 // ;; 1
426 a->nop(); // 5
427 a->fmr(F6, F6); // 6
428 a->fmr(F7, F7); // 7
429 a->endgroup(); // 8
430 // ------- sector 8 ------------
431
432 // ;; 2
433 a->nop(); // 9
434 a->nop(); // 10
435 a->fmr(F8, F8); // 11
436 a->fmr(F9, F9); // 12
437
438 // ;; 3
439 a->nop(); // 13
440 a->fmr(F10, F10); // 14
441 a->fmr(F11, F11); // 15
442 a->endgroup(); // 16
443 // -------- sector 16 -------------
444
445 // ;; 4
446 a->nop(); // 17
447 a->nop(); // 18
448 a->fmr(F15, F15); // 19
449 a->fmr(F16, F16); // 20
450
451 // ;; 5
452 a->nop(); // 21
453 a->fmr(F17, F17); // 22
454 a->fmr(F18, F18); // 23
455 a->endgroup(); // 24
456 // ------- sector 24 ------------
457
458 // ;; 6
459 a->nop(); // 25
460 a->nop(); // 26
461 a->fmr(F19, F19); // 27
462 a->fmr(F20, F20); // 28
463
464 // ;; 7
465 a->nop(); // 29
466 a->fmr(F21, F21); // 30
467 a->fmr(F22, F22); // 31
468 a->brnop0(); // 32
469
470 // ------- sector 32 ------------
471 }
472
473 // ;; 8
474 a->cmpdi(CCR0, R4, unroll); // 33
475 a->bge(CCR0, l1); // 34
476 a->blr();
477
478 // Emit code.
479 void (*test2)() = (void(*)())(void *)a->function_entry();
480 // uint32_t *code = (uint32_t *)a->pc();
481
482 Label l2;
483
484 a->li(R4, 1);
485 a->sldi(R4, R4, 28);
486 a->b(l2);
487 a->align(CodeEntryAlignment);
488
489 a->bind(l2);
490
491 for (int i = 0; i < unroll; i++) {
492 // Schleife 2
493 // ------- sector 0 ------------
494 // ;; 0
495 a->brnop0(); // 1
496 a->nop(); // 2
497 //a->cmpdi(CCR0, R4, unroll);
498 a->fpnop0(); // 3
499 a->fpnop1(); // 4
500 a->addi(R4,R4, -1); // 5
501
502 // ;; 1
503
504 a->nop(); // 6
505 a->fmr(F6, F6); // 7
506 a->fmr(F7, F7); // 8
507 // ------- sector 8 ---------------
508
509 // ;; 2
510 a->endgroup(); // 9
511
512 // ;; 3
513 a->nop(); // 10
514 a->nop(); // 11
515 a->fmr(F8, F8); // 12
516
517 // ;; 4
518 a->fmr(F9, F9); // 13
519 a->nop(); // 14
520 a->fmr(F10, F10); // 15
521
522 // ;; 5
523 a->fmr(F11, F11); // 16
524 // -------- sector 16 -------------
525
526 // ;; 6
527 a->endgroup(); // 17
528
529 // ;; 7
530 a->nop(); // 18
531 a->nop(); // 19
532 a->fmr(F15, F15); // 20
533
534 // ;; 8
535 a->fmr(F16, F16); // 21
536 a->nop(); // 22
537 a->fmr(F17, F17); // 23
538
539 // ;; 9
540 a->fmr(F18, F18); // 24
541 // -------- sector 24 -------------
542
543 // ;; 10
544 a->endgroup(); // 25
545
546 // ;; 11
547 a->nop(); // 26
548 a->nop(); // 27
549 a->fmr(F19, F19); // 28
550
551 // ;; 12
552 a->fmr(F20, F20); // 29
553 a->nop(); // 30
554 a->fmr(F21, F21); // 31
555
556 // ;; 13
557 a->fmr(F22, F22); // 32
558 }
559
560 // -------- sector 32 -------------
561 // ;; 14
562 a->cmpdi(CCR0, R4, unroll); // 33
563 a->bge(CCR0, l2); // 34
564
565 a->blr();
566 uint32_t *code_end = (uint32_t *)a->pc();
567 a->flush();
568
569 double loop1_seconds,loop2_seconds, rel_diff;
570 uint64_t start1, stop1;
571
572 start1 = os::current_thread_cpu_time(false);
573 (*test1)();
574 stop1 = os::current_thread_cpu_time(false);
575 loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0);
576
577
578 start1 = os::current_thread_cpu_time(false);
579 (*test2)();
580 stop1 = os::current_thread_cpu_time(false);
581
582 loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0);
583
584 rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100;
585
586 if (PrintAssembly) {
587 ttyLocker ttyl;
588 tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
589 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
590 tty->print_cr("Time loop1 :%f", loop1_seconds);
591 tty->print_cr("Time loop2 :%f", loop2_seconds);
592 tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff);
593
594 if (rel_diff > 12.0) {
595 tty->print_cr("Section Size 8 Instructions");
596 } else{
597 tty->print_cr("Section Size 32 Instructions or Power5");
598 }
599 }
600
601 #if 0 // TODO: PPC port
602 // Set sector size (if not set explicitly).
603 if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) {
604 if (rel_diff > 12.0) {
605 PdScheduling::power6SectorSize = 0x20;
606 } else {
607 PdScheduling::power6SectorSize = 0x80;
608 }
609 } else if (Power6SectorSize128PPC64) {
610 PdScheduling::power6SectorSize = 0x80;
611 } else {
612 PdScheduling::power6SectorSize = 0x20;
613 }
614 #endif
615 if (UsePower6SchedulerPPC64) Unimplemented();
616 }
617 #endif // COMPILER2
618
619 void VM_Version::determine_features() {
620 #if defined(ABI_ELFv2)
621 // 1 InstWord per call for the blr instruction.
622 const int code_size = (num_features+1+2*1)*BytesPerInstWord;
623 #else
624 // 7 InstWords for each call (function descriptor + blr instruction).
625 const int code_size = (num_features+1+2*7)*BytesPerInstWord;
626 #endif
627 int features = 0;
628
629 // create test area
630 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size).
631 char test_area[BUFFER_SIZE];
632 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1];
633
634 // Allocate space for the code.
635 ResourceMark rm;
636 CodeBuffer cb("detect_cpu_features", code_size, 0);
637 MacroAssembler* a = new MacroAssembler(&cb);
638
639 // Must be set to true so we can generate the test code.
640 _features = VM_Version::all_features_m;
641
642 // Emit code.
643 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
644 uint32_t *code = (uint32_t *)a->pc();
645 // Don't use R0 in ldarx.
646 // Keep R3_ARG1 unmodified, it contains &field (see below).
647 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
648 a->fsqrt(F3, F4); // code[0] -> fsqrt_m
649 a->fsqrts(F3, F4); // code[1] -> fsqrts_m
650 a->isel(R7, R5, R6, 0); // code[2] -> isel_m
651 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m
652 a->cmpb(R7, R5, R6); // code[4] -> cmpb
653 a->popcntb(R7, R5); // code[5] -> popcntb
654 a->popcntw(R7, R5); // code[6] -> popcntw
655 a->fcfids(F3, F4); // code[7] -> fcfids
656 a->vand(VR0, VR0, VR0); // code[8] -> vand
657 // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16
658 a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9] -> lqarx_m
659 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher
660 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb
661 a->tcheck(0); // code[12] -> tcheck
662 a->mfdscr(R0); // code[13] -> mfdscr
663 a->lxvd2x(VSR0, R3_ARG1); // code[14] -> vsx
664 a->ldbrx(R7, R3_ARG1, R4_ARG2); // code[15] -> ldbrx
665 a->stdbrx(R7, R3_ARG1, R4_ARG2); // code[16] -> stdbrx
666 a->blr();
667
668 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
669 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
670 a->dcbz(R3_ARG1); // R3_ARG1 = addr
671 a->blr();
672
673 uint32_t *code_end = (uint32_t *)a->pc();
674 a->flush();
675 _features = VM_Version::unknown_m;
676
677 // Print the detection code.
678 if (PrintAssembly) {
679 ttyLocker ttyl;
680 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
681 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
682 }
683
684 // Measure cache line size.
685 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
686 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle.
687 int count = 0; // count zeroed bytes
688 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++;
689 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
690 _L1_data_cache_line_size = count;
691
692 // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
693 VM_Version::_is_determine_features_test_running = true;
694 // We must align the first argument to 16 bytes because of the lqarx check.
695 (*test)(align_up((address)mid_of_test_area, 16), 0);
696 VM_Version::_is_determine_features_test_running = false;
697
698 // determine which instructions are legal.
699 int feature_cntr = 0;
700 if (code[feature_cntr++]) features |= fsqrt_m;
701 if (code[feature_cntr++]) features |= fsqrts_m;
702 if (code[feature_cntr++]) features |= isel_m;
703 if (code[feature_cntr++]) features |= lxarxeh_m;
704 if (code[feature_cntr++]) features |= cmpb_m;
705 if (code[feature_cntr++]) features |= popcntb_m;
706 if (code[feature_cntr++]) features |= popcntw_m;
707 if (code[feature_cntr++]) features |= fcfids_m;
708 if (code[feature_cntr++]) features |= vand_m;
709 if (code[feature_cntr++]) features |= lqarx_m;
710 if (code[feature_cntr++]) features |= vcipher_m;
711 if (code[feature_cntr++]) features |= vpmsumb_m;
712 if (code[feature_cntr++]) features |= tcheck_m;
713 if (code[feature_cntr++]) features |= mfdscr_m;
714 if (code[feature_cntr++]) features |= vsx_m;
715 if (code[feature_cntr++]) features |= ldbrx_m;
716 if (code[feature_cntr++]) features |= stdbrx_m;
717
718 // Print the detection code.
719 if (PrintAssembly) {
720 ttyLocker ttyl;
721 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
722 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
723 }
724
725 _features = features;
726 }
727
728 // Power 8: Configure Data Stream Control Register.
729 void VM_Version::config_dscr() {
730 // 7 InstWords for each call (function descriptor + blr instruction).
731 const int code_size = (2+2*7)*BytesPerInstWord;
732
733 // Allocate space for the code.
734 ResourceMark rm;
735 CodeBuffer cb("config_dscr", code_size, 0);
736 MacroAssembler* a = new MacroAssembler(&cb);
737
738 // Emit code.
739 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry();
740 uint32_t *code = (uint32_t *)a->pc();
741 a->mfdscr(R3);
742 a->blr();
743
744 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry();
745 a->mtdscr(R3);
746 a->blr();
747
748 uint32_t *code_end = (uint32_t *)a->pc();
749 a->flush();
750
751 // Print the detection code.
752 if (PrintAssembly) {
753 ttyLocker ttyl;
754 tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code));
755 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
756 }
757
758 // Apply the configuration if needed.
759 _dscr_val = (*get_dscr)();
760 if (Verbose) {
761 tty->print_cr("dscr value was 0x%lx" , _dscr_val);
762 }
763 bool change_requested = false;
764 if (DSCR_PPC64 != (uintx)-1) {
765 _dscr_val = DSCR_PPC64;
766 change_requested = true;
767 }
768 if (DSCR_DPFD_PPC64 <= 7) {
769 uint64_t mask = 0x7;
770 if ((_dscr_val & mask) != DSCR_DPFD_PPC64) {
771 _dscr_val = (_dscr_val & ~mask) | (DSCR_DPFD_PPC64);
772 change_requested = true;
773 }
774 }
775 if (DSCR_URG_PPC64 <= 7) {
776 uint64_t mask = 0x7 << 6;
777 if ((_dscr_val & mask) != DSCR_DPFD_PPC64 << 6) {
778 _dscr_val = (_dscr_val & ~mask) | (DSCR_URG_PPC64 << 6);
779 change_requested = true;
780 }
781 }
782 if (change_requested) {
783 (*set_dscr)(_dscr_val);
784 if (Verbose) {
785 tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)());
786 }
787 }
788 }
789
790 static uint64_t saved_features = 0;
791
792 void VM_Version::allow_all() {
793 saved_features = _features;
794 _features = all_features_m;
795 }
796
797 void VM_Version::revert() {
798 _features = saved_features;
799 }