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src/cpu/ppc/vm/c1_Defs_ppc.hpp

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rev 12310 : Reserve R30 to a cleared content register on C1 and C2 code

Several times a 0 is loaded to a register as a temporary value. This can be
improved by caching a 0 into a register.

I didn't notice a performance drop since only applying this patch showed no
drop of performance, hence there are more registers available than normally
needed and this caching technique can be applied.

Despite setting R30_zero as a dedicated register and initialized with 0 for the
C1 and C2 code, new rules for storing 0 related to stb,sth,stw,std were added.


  30 enum {
  31 #if defined(VM_LITTLE_ENDIAN)
  32   pd_lo_word_offset_in_bytes = 0,
  33   pd_hi_word_offset_in_bytes = BytesPerInt
  34 #else
  35   pd_lo_word_offset_in_bytes = BytesPerInt,
  36   pd_hi_word_offset_in_bytes = 0
  37 #endif
  38 };
  39 
  40 
  41 // Explicit rounding operations are not required to implement the strictFP mode.
  42 enum {
  43   pd_strict_fp_requires_explicit_rounding = false
  44 };
  45 
  46 
  47 // registers
  48 enum {
  49   pd_nof_cpu_regs_frame_map = 32,              // Number of registers used during code emission.
  50   pd_nof_caller_save_cpu_regs_frame_map = 27,  // Number of cpu registers killed by calls. (At least R3_ARG1 ... R10_ARG8, but using all like C2.)
  51   pd_nof_cpu_regs_reg_alloc = 27,              // Number of registers that are visible to register allocator.
  52   pd_nof_cpu_regs_linearscan = 32,             // Number of registers visible linear scan.
  53   pd_first_callee_saved_reg = pd_nof_caller_save_cpu_regs_frame_map,
  54   pd_last_callee_saved_reg = pd_nof_cpu_regs_reg_alloc - 1,
  55   pd_first_cpu_reg = 0,
  56   pd_last_cpu_reg = pd_nof_cpu_regs_reg_alloc - 1,
  57 
  58   pd_nof_fpu_regs_frame_map = 32,              // Number of registers used during code emission.
  59   pd_nof_caller_save_fpu_regs_frame_map = 32,  // Number of fpu registers killed by calls.
  60   pd_nof_fpu_regs_reg_alloc = 32,              // Number of registers that are visible to register allocator.
  61   pd_nof_fpu_regs_linearscan = 32,             // Number of registers visible to linear scan.
  62   pd_first_fpu_reg = pd_nof_cpu_regs_frame_map,
  63   pd_last_fpu_reg =  pd_nof_cpu_regs_frame_map + pd_nof_fpu_regs_reg_alloc - 1,
  64 
  65   pd_nof_xmm_regs_linearscan = 0,
  66   pd_nof_caller_save_xmm_regs = 0,
  67   pd_first_xmm_reg = -1,
  68   pd_last_xmm_reg = -1
  69 };
  70 
  71 // For debug info: a float value in a register is saved in single precision by runtime stubs.



  30 enum {
  31 #if defined(VM_LITTLE_ENDIAN)
  32   pd_lo_word_offset_in_bytes = 0,
  33   pd_hi_word_offset_in_bytes = BytesPerInt
  34 #else
  35   pd_lo_word_offset_in_bytes = BytesPerInt,
  36   pd_hi_word_offset_in_bytes = 0
  37 #endif
  38 };
  39 
  40 
  41 // Explicit rounding operations are not required to implement the strictFP mode.
  42 enum {
  43   pd_strict_fp_requires_explicit_rounding = false
  44 };
  45 
  46 
  47 // registers
  48 enum {
  49   pd_nof_cpu_regs_frame_map = 32,              // Number of registers used during code emission.
  50   pd_nof_caller_save_cpu_regs_frame_map = 26,  // Number of cpu registers killed by calls. (At least R3_ARG1 ... R10_ARG8, but using all like C2.)
  51   pd_nof_cpu_regs_reg_alloc = 26,              // Number of registers that are visible to register allocator.
  52   pd_nof_cpu_regs_linearscan = 32,             // Number of registers visible linear scan.
  53   pd_first_callee_saved_reg = pd_nof_caller_save_cpu_regs_frame_map,
  54   pd_last_callee_saved_reg = pd_nof_cpu_regs_reg_alloc - 1,
  55   pd_first_cpu_reg = 0,
  56   pd_last_cpu_reg = pd_nof_cpu_regs_reg_alloc - 1,
  57 
  58   pd_nof_fpu_regs_frame_map = 32,              // Number of registers used during code emission.
  59   pd_nof_caller_save_fpu_regs_frame_map = 32,  // Number of fpu registers killed by calls.
  60   pd_nof_fpu_regs_reg_alloc = 32,              // Number of registers that are visible to register allocator.
  61   pd_nof_fpu_regs_linearscan = 32,             // Number of registers visible to linear scan.
  62   pd_first_fpu_reg = pd_nof_cpu_regs_frame_map,
  63   pd_last_fpu_reg =  pd_nof_cpu_regs_frame_map + pd_nof_fpu_regs_reg_alloc - 1,
  64 
  65   pd_nof_xmm_regs_linearscan = 0,
  66   pd_nof_caller_save_xmm_regs = 0,
  67   pd_first_xmm_reg = -1,
  68   pd_last_xmm_reg = -1
  69 };
  70 
  71 // For debug info: a float value in a register is saved in single precision by runtime stubs.
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