Cdiffs Udiffs Sdiffs Frames Old New ----- Raw src/cpu/ppc/vm/c1_Defs_ppc.hpp

rev 12310 : Reserve R30 to a cleared content register on C1 and C2 code

Several times a 0 is loaded to a register as a temporary value. This can be
improved by caching a 0 into a register.

I didn't notice a performance drop since only applying this patch showed no
drop of performance, hence there are more registers available than normally
needed and this caching technique can be applied.

Despite setting R30_zero as a dedicated register and initialized with 0 for the
C1 and C2 code, new rules for storing 0 related to stb,sth,stw,std were added.

2 lines changed: 0 ins; 0 del; 2 mod; 74 unchg

Cdiffs Udiffs Sdiffs Frames Old New ----- Raw src/cpu/ppc/vm/c1_FrameMap_ppc.cpp

rev 12310 : Reserve R30 to a cleared content register on C1 and C2 code

Several times a 0 is loaded to a register as a temporary value. This can be
improved by caching a 0 into a register.

I didn't notice a performance drop since only applying this patch showed no
drop of performance, hence there are more registers available than normally
needed and this caching technique can be applied.

Despite setting R30_zero as a dedicated register and initialized with 0 for the
C1 and C2 code, new rules for storing 0 related to stb,sth,stw,std were added.

4 lines changed: 0 ins; 0 del; 4 mod; 390 unchg

Cdiffs Udiffs Sdiffs Frames Old New ----- Raw src/cpu/ppc/vm/c1_FrameMap_ppc.hpp

rev 12310 : Reserve R30 to a cleared content register on C1 and C2 code

Several times a 0 is loaded to a register as a temporary value. This can be
improved by caching a 0 into a register.

I didn't notice a performance drop since only applying this patch showed no
drop of performance, hence there are more registers available than normally
needed and this caching technique can be applied.

Despite setting R30_zero as a dedicated register and initialized with 0 for the
C1 and C2 code, new rules for storing 0 related to stb,sth,stw,std were added.

4 lines changed: 1 ins; 0 del; 3 mod; 199 unchg

Cdiffs Udiffs Sdiffs Frames Old New ----- Raw src/cpu/ppc/vm/ppc.ad

rev 12310 : Reserve R30 to a cleared content register on C1 and C2 code

Several times a 0 is loaded to a register as a temporary value. This can be
improved by caching a 0 into a register.

I didn't notice a performance drop since only applying this patch showed no
drop of performance, hence there are more registers available than normally
needed and this caching technique can be applied.

Despite setting R30_zero as a dedicated register and initialized with 0 for the
C1 and C2 code, new rules for storing 0 related to stb,sth,stw,std were added.

84 lines changed: 57 ins; 8 del; 19 mod; 13283 unchg

Cdiffs Udiffs Sdiffs Frames Old New ----- Raw src/cpu/ppc/vm/register_ppc.hpp

rev 12310 : Reserve R30 to a cleared content register on C1 and C2 code

Several times a 0 is loaded to a register as a temporary value. This can be
improved by caching a 0 into a register.

I didn't notice a performance drop since only applying this patch showed no
drop of performance, hence there are more registers available than normally
needed and this caching technique can be applied.

Despite setting R30_zero as a dedicated register and initialized with 0 for the
C1 and C2 code, new rules for storing 0 related to stb,sth,stw,std were added.

2 lines changed: 2 ins; 0 del; 0 mod; 752 unchg

Cdiffs Udiffs Sdiffs Frames Old New ----- Raw src/cpu/ppc/vm/stubGenerator_ppc.cpp

rev 12310 : Reserve R30 to a cleared content register on C1 and C2 code

Several times a 0 is loaded to a register as a temporary value. This can be
improved by caching a 0 into a register.

I didn't notice a performance drop since only applying this patch showed no
drop of performance, hence there are more registers available than normally
needed and this caching technique can be applied.

Despite setting R30_zero as a dedicated register and initialized with 0 for the
C1 and C2 code, new rules for storing 0 related to stb,sth,stw,std were added.

3 lines changed: 3 ins; 0 del; 0 mod; 3448 unchg

Cdiffs Udiffs Sdiffs Frames Old New ----- Raw src/cpu/ppc/vm/templateInterpreterGenerator_ppc.cpp

rev 12310 : Reserve R30 to a cleared content register on C1 and C2 code

Several times a 0 is loaded to a register as a temporary value. This can be
improved by caching a 0 into a register.

I didn't notice a performance drop since only applying this patch showed no
drop of performance, hence there are more registers available than normally
needed and this caching technique can be applied.

Despite setting R30_zero as a dedicated register and initialized with 0 for the
C1 and C2 code, new rules for storing 0 related to stb,sth,stw,std were added.

1 line changed: 1 ins; 0 del; 0 mod; 2357 unchg

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