src/cpu/ppc/vm/c1_Defs_ppc.hpp

rev 12310 : Reserve R30 to a cleared content register on C1 and C2 code

Several times a 0 is loaded to a register as a temporary value. This can be
improved by caching a 0 into a register.

I didn't notice a performance drop since only applying this patch showed no
drop of performance, hence there are more registers available than normally
needed and this caching technique can be applied.

Despite setting R30_zero as a dedicated register and initialized with 0 for the
C1 and C2 code, new rules for storing 0 related to stb,sth,stw,std were added.

@@ -45,12 +45,12 @@
 
 
 // registers
 enum {
   pd_nof_cpu_regs_frame_map = 32,              // Number of registers used during code emission.
-  pd_nof_caller_save_cpu_regs_frame_map = 27,  // Number of cpu registers killed by calls. (At least R3_ARG1 ... R10_ARG8, but using all like C2.)
-  pd_nof_cpu_regs_reg_alloc = 27,              // Number of registers that are visible to register allocator.
+  pd_nof_caller_save_cpu_regs_frame_map = 26,  // Number of cpu registers killed by calls. (At least R3_ARG1 ... R10_ARG8, but using all like C2.)
+  pd_nof_cpu_regs_reg_alloc = 26,              // Number of registers that are visible to register allocator.
   pd_nof_cpu_regs_linearscan = 32,             // Number of registers visible linear scan.
   pd_first_callee_saved_reg = pd_nof_caller_save_cpu_regs_frame_map,
   pd_last_callee_saved_reg = pd_nof_cpu_regs_reg_alloc - 1,
   pd_first_cpu_reg = 0,
   pd_last_cpu_reg = pd_nof_cpu_regs_reg_alloc - 1,