src/cpu/ppc/vm/c1_FrameMap_ppc.hpp

rev 12310 : Reserve R30 to a cleared content register on C1 and C2 code

Several times a 0 is loaded to a register as a temporary value. This can be
improved by caching a 0 into a register.

I didn't notice a performance drop since only applying this patch showed no
drop of performance, hence there are more registers available than normally
needed and this caching technique can be applied.

Despite setting R30_zero as a dedicated register and initialized with 0 for the
C1 and C2 code, new rules for storing 0 related to stb,sth,stw,std were added.

*** 98,108 ****
    static LIR_Opr R26_oop_opr;
    static LIR_Opr R27_oop_opr;
    static LIR_Opr R28_oop_opr;
    static LIR_Opr R29_oop_opr;
    //R29: TOC register. Not an oop.
!   static LIR_Opr R30_oop_opr;
    static LIR_Opr R31_oop_opr;
  
    static LIR_Opr  R0_metadata_opr;
    //R1: Stack pointer. Not metadata.
    static LIR_Opr  R2_metadata_opr;
--- 98,108 ----
    static LIR_Opr R26_oop_opr;
    static LIR_Opr R27_oop_opr;
    static LIR_Opr R28_oop_opr;
    static LIR_Opr R29_oop_opr;
    //R29: TOC register. Not an oop.
!   //R30: R30_zero. Not an oop.
    static LIR_Opr R31_oop_opr;
  
    static LIR_Opr  R0_metadata_opr;
    //R1: Stack pointer. Not metadata.
    static LIR_Opr  R2_metadata_opr;
*** 131,141 ****
    static LIR_Opr R25_metadata_opr;
    static LIR_Opr R26_metadata_opr;
    static LIR_Opr R27_metadata_opr;
    static LIR_Opr R28_metadata_opr;
    //R29: TOC register. Not metadata.
!   static LIR_Opr R30_metadata_opr;
    static LIR_Opr R31_metadata_opr;
  
    static LIR_Opr SP_opr;
  
    static LIR_Opr R0_long_opr;
--- 131,141 ----
    static LIR_Opr R25_metadata_opr;
    static LIR_Opr R26_metadata_opr;
    static LIR_Opr R27_metadata_opr;
    static LIR_Opr R28_metadata_opr;
    //R29: TOC register. Not metadata.
!   //R30: R30_zero. Not metadata.
    static LIR_Opr R31_metadata_opr;
  
    static LIR_Opr SP_opr;
  
    static LIR_Opr R0_long_opr;
*** 195,202 ****
    //  R0: scratch
    //  R1: sp
    // R13: system thread id
    // R16: java thread
    // R29: global TOC
!   static bool reg_needs_save(Register r) { return r != R0 && r != R1 && r != R13 && r != R16 && r != R29; }
  
  #endif // CPU_PPC_VM_C1_FRAMEMAP_PPC_HPP
--- 195,203 ----
    //  R0: scratch
    //  R1: sp
    // R13: system thread id
    // R16: java thread
    // R29: global TOC
!   // R30: R30_zero
!   static bool reg_needs_save(Register r) { return r != R0 && r != R1 && r != R13 && r != R16 && r != R29 && r != R30; }
  
  #endif // CPU_PPC_VM_C1_FRAMEMAP_PPC_HPP