src/cpu/ppc/vm/register_ppc.hpp

rev 12310 : Reserve R30 to a cleared content register on C1 and C2 code

Several times a 0 is loaded to a register as a temporary value. This can be
improved by caching a 0 into a register.

I didn't notice a performance drop since only applying this patch showed no
drop of performance, hence there are more registers available than normally
needed and this caching technique can be applied.

Despite setting R30_zero as a dedicated register and initialized with 0 for the
C1 and C2 code, new rules for storing 0 related to stb,sth,stw,std were added.

*** 712,721 ****
--- 712,722 ----
  REGISTER_DECLARATION(Register, R24_dispatch_addr,     R24);
  REGISTER_DECLARATION(Register, R25_templateTableBase, R25);
  REGISTER_DECLARATION(Register, R26_monitor,           R26);
  REGISTER_DECLARATION(Register, R27_constPoolCache,    R27);
  REGISTER_DECLARATION(Register, R28_mdx,               R28);
+ REGISTER_DECLARATION(Register, R30_zero,              R30);
  
  REGISTER_DECLARATION(Register, R19_inline_cache_reg, R19);
  REGISTER_DECLARATION(Register, R29_TOC, R29);
  
  #ifndef DONT_USE_REGISTER_DEFINES
*** 734,743 ****
--- 735,745 ----
  #define R24_dispatch_addr     AS_REGISTER(Register, R24)
  #define R25_templateTableBase AS_REGISTER(Register, R25)
  #define R26_monitor           AS_REGISTER(Register, R26)
  #define R27_constPoolCache    AS_REGISTER(Register, R27)
  #define R28_mdx               AS_REGISTER(Register, R28)
+ #define R30_zero              AS_REGISTER(Register, R30)
  
  #define R19_inline_cache_reg AS_REGISTER(Register, R19)
  #define R29_TOC AS_REGISTER(Register, R29)
  #endif