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src/cpu/ppc/vm/register_ppc.hpp

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rev 12310 : Reserve R30 to a cleared content register on C1 and C2 code

Several times a 0 is loaded to a register as a temporary value. This can be
improved by caching a 0 into a register.

I didn't notice a performance drop since only applying this patch showed no
drop of performance, hence there are more registers available than normally
needed and this caching technique can be applied.

Despite setting R30_zero as a dedicated register and initialized with 0 for the
C1 and C2 code, new rules for storing 0 related to stb,sth,stw,std were added.


 697 #define R23_method_handle AS_REGISTER(Register, R23)
 698 #endif
 699 
 700 // Temporary registers to be used within frame manager. We can use
 701 // the non-volatiles because the call stub has saved them.
 702 // Use only non-volatile registers in order to keep values across C-calls.
 703 REGISTER_DECLARATION(Register, R21_tmp1, R21);
 704 REGISTER_DECLARATION(Register, R22_tmp2, R22);
 705 REGISTER_DECLARATION(Register, R23_tmp3, R23);
 706 REGISTER_DECLARATION(Register, R24_tmp4, R24);
 707 REGISTER_DECLARATION(Register, R25_tmp5, R25);
 708 REGISTER_DECLARATION(Register, R26_tmp6, R26);
 709 REGISTER_DECLARATION(Register, R27_tmp7, R27);
 710 REGISTER_DECLARATION(Register, R28_tmp8, R28);
 711 REGISTER_DECLARATION(Register, R29_tmp9, R29);
 712 REGISTER_DECLARATION(Register, R24_dispatch_addr,     R24);
 713 REGISTER_DECLARATION(Register, R25_templateTableBase, R25);
 714 REGISTER_DECLARATION(Register, R26_monitor,           R26);
 715 REGISTER_DECLARATION(Register, R27_constPoolCache,    R27);
 716 REGISTER_DECLARATION(Register, R28_mdx,               R28);

 717 
 718 REGISTER_DECLARATION(Register, R19_inline_cache_reg, R19);
 719 REGISTER_DECLARATION(Register, R29_TOC, R29);
 720 
 721 #ifndef DONT_USE_REGISTER_DEFINES
 722 #define R21_tmp1         AS_REGISTER(Register, R21)
 723 #define R22_tmp2         AS_REGISTER(Register, R22)
 724 #define R23_tmp3         AS_REGISTER(Register, R23)
 725 #define R24_tmp4         AS_REGISTER(Register, R24)
 726 #define R25_tmp5         AS_REGISTER(Register, R25)
 727 #define R26_tmp6         AS_REGISTER(Register, R26)
 728 #define R27_tmp7         AS_REGISTER(Register, R27)
 729 #define R28_tmp8         AS_REGISTER(Register, R28)
 730 #define R29_tmp9         AS_REGISTER(Register, R29)
 731 //    Lmonitors  : monitor pointer
 732 //    LcpoolCache: constant pool cache
 733 //    mdx: method data index
 734 #define R24_dispatch_addr     AS_REGISTER(Register, R24)
 735 #define R25_templateTableBase AS_REGISTER(Register, R25)
 736 #define R26_monitor           AS_REGISTER(Register, R26)
 737 #define R27_constPoolCache    AS_REGISTER(Register, R27)
 738 #define R28_mdx               AS_REGISTER(Register, R28)

 739 
 740 #define R19_inline_cache_reg AS_REGISTER(Register, R19)
 741 #define R29_TOC AS_REGISTER(Register, R29)
 742 #endif
 743 
 744 // Scratch registers are volatile.
 745 REGISTER_DECLARATION(Register, R11_scratch1, R11);
 746 REGISTER_DECLARATION(Register, R12_scratch2, R12);
 747 #ifndef DONT_USE_REGISTER_DEFINES
 748 #define R11_scratch1   AS_REGISTER(Register, R11)
 749 #define R12_scratch2   AS_REGISTER(Register, R12)
 750 #endif
 751 
 752 #endif // CPU_PPC_VM_REGISTER_PPC_HPP



 697 #define R23_method_handle AS_REGISTER(Register, R23)
 698 #endif
 699 
 700 // Temporary registers to be used within frame manager. We can use
 701 // the non-volatiles because the call stub has saved them.
 702 // Use only non-volatile registers in order to keep values across C-calls.
 703 REGISTER_DECLARATION(Register, R21_tmp1, R21);
 704 REGISTER_DECLARATION(Register, R22_tmp2, R22);
 705 REGISTER_DECLARATION(Register, R23_tmp3, R23);
 706 REGISTER_DECLARATION(Register, R24_tmp4, R24);
 707 REGISTER_DECLARATION(Register, R25_tmp5, R25);
 708 REGISTER_DECLARATION(Register, R26_tmp6, R26);
 709 REGISTER_DECLARATION(Register, R27_tmp7, R27);
 710 REGISTER_DECLARATION(Register, R28_tmp8, R28);
 711 REGISTER_DECLARATION(Register, R29_tmp9, R29);
 712 REGISTER_DECLARATION(Register, R24_dispatch_addr,     R24);
 713 REGISTER_DECLARATION(Register, R25_templateTableBase, R25);
 714 REGISTER_DECLARATION(Register, R26_monitor,           R26);
 715 REGISTER_DECLARATION(Register, R27_constPoolCache,    R27);
 716 REGISTER_DECLARATION(Register, R28_mdx,               R28);
 717 REGISTER_DECLARATION(Register, R30_zero,              R30);
 718 
 719 REGISTER_DECLARATION(Register, R19_inline_cache_reg, R19);
 720 REGISTER_DECLARATION(Register, R29_TOC, R29);
 721 
 722 #ifndef DONT_USE_REGISTER_DEFINES
 723 #define R21_tmp1         AS_REGISTER(Register, R21)
 724 #define R22_tmp2         AS_REGISTER(Register, R22)
 725 #define R23_tmp3         AS_REGISTER(Register, R23)
 726 #define R24_tmp4         AS_REGISTER(Register, R24)
 727 #define R25_tmp5         AS_REGISTER(Register, R25)
 728 #define R26_tmp6         AS_REGISTER(Register, R26)
 729 #define R27_tmp7         AS_REGISTER(Register, R27)
 730 #define R28_tmp8         AS_REGISTER(Register, R28)
 731 #define R29_tmp9         AS_REGISTER(Register, R29)
 732 //    Lmonitors  : monitor pointer
 733 //    LcpoolCache: constant pool cache
 734 //    mdx: method data index
 735 #define R24_dispatch_addr     AS_REGISTER(Register, R24)
 736 #define R25_templateTableBase AS_REGISTER(Register, R25)
 737 #define R26_monitor           AS_REGISTER(Register, R26)
 738 #define R27_constPoolCache    AS_REGISTER(Register, R27)
 739 #define R28_mdx               AS_REGISTER(Register, R28)
 740 #define R30_zero              AS_REGISTER(Register, R30)
 741 
 742 #define R19_inline_cache_reg AS_REGISTER(Register, R19)
 743 #define R29_TOC AS_REGISTER(Register, R29)
 744 #endif
 745 
 746 // Scratch registers are volatile.
 747 REGISTER_DECLARATION(Register, R11_scratch1, R11);
 748 REGISTER_DECLARATION(Register, R12_scratch2, R12);
 749 #ifndef DONT_USE_REGISTER_DEFINES
 750 #define R11_scratch1   AS_REGISTER(Register, R11)
 751 #define R12_scratch2   AS_REGISTER(Register, R12)
 752 #endif
 753 
 754 #endif // CPU_PPC_VM_REGISTER_PPC_HPP
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